The present invention is directed to a technique in which a conventional NEC 7220 graphic display controller chip accesses three bit planes arranged in a single memory bank of sixteen 64K RAM or memory chips to control the color data to a color monitor made up of approximately 325K pixels.
In a conventional computer graphic system, the display is divided into many tiny dots that can be set to some arbitrary color by a logic system. These dots are called "pixels," which is an abbreviation for "picture elements." Conventionally each pixel includes either three or nine inputs mixtures of which provide different colors. Each pixel is represented in the memory that determines the picture by a series of information bits, which in turn determine the color of any pixel. If each pixel has three bits in memory, then the pixel can ultimately show any one of eight different colors (there are eight combinations of three bits). In the case of nine bit pixels, each pixel can be one of 512 colors.
The memory used to store the picture is called the "frame buffer" which is conceptually a plane of memory bits laid out in a pattern that is similar to the pattern of the pixels on the screen. One conventional screen utilizes a plane of 672 pixels or bits horizontally by 480 pixels or bits vertically. This plane of bits in memory is called a bit plane, since it includes one bit of information for every pixel in the screen. To represent all the bits that each pixel actually receives, the bit planes are imagined to be stacked one after the other, so that each pixel location has as many bits as the stack of bit planes is deep. For example, in the case of a three bit pixel, the frame buffer would include a stack of three bit planes, and in the case of a nine bit pixel, the frame buffer would include a stack of nine bit planes.
In conventional techniques for processing data from a frame buffer to pixels, there is a bit plane provided for each pixel input. Thus, for pixels which are operated by three bits of information (representing three primary colors), there are three bit planes. Accordingly, for pixels that are operated by nine bits of information, there are nine bit planes. Each bit plane has a set of output or transfer lines to its shift register.
It is now conventional in the industry to use 64K RAM's and an NEC 7220 graphic display control chip (GDC). The NEC 7220 graphic display control is designed to work only with sixteen (possibly thirty-two) bit memory. (Other GDC's may require N-bits) Since conventional 64K RAMS are only one bit wide (one output line per address), it is necessary to have sixteen (or N) output or transfer lines and thus at least sixteen memory chips for each bit plane. This provides a memory bank of 1024K bits. However, a 672.times.480 color monitor requires only approximately 325K bits in each bit plane to satisfactorily provide sufficient operational information. Thus, the frame buffer has approximately 70% of its memory capacity unused.
A second consideration of the conventional setup has to do with time. The NEC 7220 graphic display control chip utilizes an 800 nanosecond display cycle, which means that a new address is generated each 800 nanoseconds. However, only approximately 200 nanoseconds are required to actually address, read, and load a data word of N-bits from the bit plane into the shift register (referred to as a "memory cycle"). Therefore, again, there is approximately 75% of each display cycle of the NEC 7220 control chip which is wasted time.
Thus, there is both wasted time and wasted memory capacity in a conventional graphic data processing technique which utilizes the NEC 7220 control chip and conventional 64K bit wide random access memory chips (RAM). It is desirable, however, to continue using the aforedescribed control chip and memory chips in computer color graphic systems because they are well known, well recognized, and standard in the industry. However, according to the conventional technique the total number of memory chips in a system which operates a 627.times.480 pixel color minotor would be sixteen (the minimum number per bit plane) times the number of bit planes, or forty-eight memory chips for a three bit plane machine. This is expensive from the standpoint of excessive cost of chips, excessive printed circuit boards, and wasted space. The present invention, therefore, is directed to a technique for using the wasted address space and time, so that a three bit-plane system can operate with only (16) 64K RAM chips.
To accomplish this technique, and in accordance with the present invention, the three bit planes are arranged one after the other in the address space of the frame buffer. Approximately one-third of the data bits from each memory chip is located in each bit plane. Without more, however, each read of the memory would provide data from only one bit-plane, as the NEC 7220 only provides one address for each display cycle. Therefore, since there is sufficient times during each display cycle to perform three reads of the video memory (memory cycles), in the present invention, essentially what is done is to read the first bit plane and latch the data, rather than transferring it to a shift register. Next, a constant is added to the address signal from the NEC 7220 that then locates and reads a data word from the second bit plane, which is then latched without being transferred to the shift register. Finally, a third, higher constant is added to the original address signal from the NEC 7220, which addresses the third bit plane, from which a data word is read. At this time, the three words from three separate bit planes, which have been read during the same display cycle, are loaded into the shift registers simultaneously.
The mechanics of performing these three read cycles are as follows: the row address is strobed into the memory bank as usual, followed by the column address for the first read. After the first memory cycle a second column address is strobed into the memory bank for the second read, and then after the second memory cycle a third column address. The second and third column addresses are generated by adding a constant to the original address signal by an adder means connected between the NEC 7220 and the memory bank.
It should be recognized that while, for the most part, the description has been and will be directed to the processing of data for a three bit pixel system, by duplicating the described technique in three parallel circuits, the same technique could be utilized to advantage in the processing of data for nine bit pixels. Also, if other graphic display control chips operated on N-bits, and if N-memory chips far exceed the number of data bits for each bit plane, the instant invention would be applicable.
Attention is called to U.S. Pat. No. 4,303,986 to Lans, in which some attempt is made to combine data from a memory bank to shift registers to conserve time. What Lans actually does is to group sixteen transfers from a memory bank in to four groups of four bit nibbles, each nibble being transferred simultaneously to one of four separate shift registers. This is not the same concept nor anything like the present invention.
It is therefore an object of the present invention to provide a data processing technique for computer color graphic systems which utilizes to maximum efficiency conventional memory chips, so that the number of chips and associated wiring required may be minimized.
It is a further object of the present invention to provide a data processing technique of the type described in which multiple address signals are presented to a frame buffer during each display cycle, and a data word from the memory bank read during each partial cycle, before the last partial cycle, is latched. Then all data words are loaded into shift registers simultaneously at the end of a display cycle.